`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/06/25 22:41:06
// Design Name: 
// Module Name: alu
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module alu(
    input rst,
    input [2:0] alu_op,
    input [31:0] alu_a,
    input [31:0] alu_b,
    input [1:0] branch,
    output reg [31:0] alu_c
    );
    
integer a,b;   
    
always @(*)
begin
    if (rst)
    begin
        alu_c <= 32'hzzzzzzzz;
    end
    else
    begin
        if (branch == 2'b01)
        begin
            a = alu_a;
            b = alu_b;
            alu_c <= {31'b0,(a < b)};
        end
        else if (branch == 2'b10)
        begin
           alu_c <= {31'b0,(alu_a < alu_b)}; 
        end
        else
        begin
            a = alu_a;
            b = alu_b;
            case (alu_op)
                `ADD: alu_c <= a + b;
                `SUB: alu_c <= a - b;
                `OR:  alu_c <= a | b;
                `AND: alu_c <= a & b;
                `XOR: alu_c <= a ^ b;
                `LS:  alu_c <= a << b;
                `RSL: alu_c <= a >> b;
                `RSA: alu_c <= a >>> b;
            endcase
        end
    end
end    
    
endmodule
